PACT 2018
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Limassol, Cyprus
Nov 01-04, 2018

Dates & Deadlines:

  • April 8, 2018: Abstract Deadline
  • April 15, 2018: Paper Deadline
  • April 22, 2018: Workshop and Tutorial Proposal Deadline
  • June 4-6, 2018: Author Response Period
  • June 20, 2018: Author Notification
  • June 29, 2018: ACM Student Research Competition
  • July 9, 2018: Artifact Evaluation Submission Deadline
  • Aug 3, 2018: Camera Ready Final Papers
  • September 7, 2018: Student Travel Grants
  • November 01-04, 2018: PACT 2018

PACT 2018 Information:

Call for Contributions

Program

Location

Registration


PACT 2018 Organization:


Previous PACTs:
PACT17 PACT16 PACT15 PACT14 PACT13 PACT12 PACT11 PACT10 PACT09 PACT08 PACT07 PACT06 PACT05 PACT04 PACT03 PACT02 PACT01 PACT00 PACT99

Sponsors







Address questions to: skevos [at] cs.ucy.ac.cy

The 27th International Conference on
Parallel Architectures and Compilation Techniques (PACT18)
Limassol, Cyprus
November 01-04, 2018


PACT 2018 Main Conference

The PACT 2018 tutorials and workshops will be held Saturday November 3 and Sunday November 4 see the Tutorials and Workshops Schedule for details.
The PACT 2018 technical sessions will be held Thurdsay November 1 through Saturday November 3 at the conference hotel, the Mediterranean Hotel in Limassol, Cyprus.

PACT 2018 Main Conference Day 1 - Thursday, November 1, 2018
08:00-08:30 Opening
08:30-09:30 Keynote
Keshav Pingali, University of Texas at Austin: "50 Years of Parallel programming: Ieri, Oggi, Domani*"
09:30-10:00 BREAK
10:00-11:30 Session 1a: Emerging Applications & Systems
  • Massively Parallel Skyline Computation For Processing-In-Memory Architectures
    Vasileios Zois (University of California, Riverside), Divya Gupta (UPMEM, SAS), Vassilis J. Tsotras, Walid A. Najjar (University of California, Riverside), Jean-Francois Roy (UPMEM, SAS)
  • Data Motifs: A Lens Towards Fully Understanding Big Data and AI Workloads
    Wanling Gao, Jianfeng Zhan, Lei Wang, Chunjie Luo, Daoyi Zheng, Fei Tang, Biwei Xie, Chen Zheng, Xu Wen, Xiwen He (ICT, CAS), Hainan Ye (BAFST), and Rui Ren (ICT, CAS)
  • Performance Extraction and Suitability Analysis of Multi- and Many-core Architectures for Next Generation Sequencing Secondary Analysis
    Sanchit Misra (Intel Corporation), Tony Pan (Georgia Institute of Technology), Kanak Mahadik (Adobe Systems), George Powley, Priya N. Vaidya (Intel Corporation), Md. Vasimuddin (Indian Institute of Technology Bombay), Srinivas Aluru (Georgia Institute of Technology)

Session 1b: Memory Systems
  • Synergistic Cache Layout for Reuse and Compression
    Biswabandan Panda (IIT Kanpur), Andre Seznec (INRIA Rennes)
  • HyPart: A Hybrid Technique for Practical Memory Bandwidth Partitioning on Commodity Servers
    Jinsu Park, Seongbeom Park, Myeonggyun Han, Jihoon Hyun, Woongki Baek (UNIST)
  • EAR: ECC-Aided Refresh Reduction through 2-D Zero Compression
    Jeongkyu Hong, Hyeonggyu Kim, Soontae Kim (KAIST)
11:30-13:00 LUNCH
13:00-14:30 Session 2a: Graph Processing
  • Log(Graph): A Near-Optimal High-Performance Graph Representation
    Maciej Besta, Dimitri Stanojevic, Tijana Zivic, Jagpreet Singh, Maurice Hörold, Torsten Hoefler (ETH Zurich)
  • An Efficient Graph Accelerator with Parallel Data Conflict Management
    Pengcheng Yao, Long Zheng, Xiaofei Liao, Hai Jin (Huazhong University of Science and Technology), Bingsheng He (National University of Singapore)
  • GraphPhi: Efficient Parallel Graph Processing on Emerging Throughput-oriented Architectures
    Zhen Peng, Alexander Powell (College of William and Mary), Bo Wu (Colorado School of Mines), Tekin Bicer (Argonne National Laboratory), Bin Ren (College of William and Mary)

Session 2b: Compiler Optimization
  • Revealing Parallel Scans and Reductions in Recurrences through Function Reconstruction
    Peng Jiang (The Ohio State University), Linchuan Chen (Google), Gagan Agrawal (The Ohio State University)
  • Compiler Assisted Coalescing
    Sooraj Puthoor (AMD, University of Wisconsin-Madison), Mikko H. Lipasti (University of Wisconsin-Madison)
  • VW-SLP: Auto-Vectorization with Adaptive Vector Width
    Vasileios Porpodas (Intel), Rodrigo C. O. Rocha (University of Edinburgh), Luis F. W. Goes (PUC Minas)
14:30-15:00 BREAK
15:00-16:30 Session 3a: Parallelization Management
  • Stencil Codes on a Vector Length Agnostic Architecture
    Adrià Armejach (Barcelona Supercomputing Center / Universitat Politècnica de Catalunya), Helena Caminal (Cornell University), Juan M. Cebrián (Barcelona Supercomputing Center), Rekai González-Alberquilla (Arm), Marc Casas, Miquel Moretó (Barcelona Supercomputing Center), Chris Adeniyi-Jones (Arm), Mateo Valero (Barcelona Supercomputing Center)
  • Maximizing System Utilization via Parallelism Management for Co-Located Parallel Applications
    Younghyun Cho, Camilo Andres Celis Guzman, Bernhard Egger (Seoul National University)
  • MemoDyn: Exploiting Weakly Consistent Data Structures for Dynamic Parallel Memoization
    Prakash Prabhu (Google), Stephen R. Beard, Sotiris Apostolakis (Princeton University), Ayal Zaks (Intel / Technion), David I. August (Princeton University)
Session 3b: Machine Learning Architectures
  • Architectural Support for Convolutional Neural Networks on Modern CPUs
    Animesh Jain, Michael A. Lauernzano (University of Michigan, Ann Arbor), Gilles Pokam (Intel), Jason Mars, Lingjia Tang (University of Michigan, Ann Arbor)
  • A Portable, Automatic Data Quantizer for Deep Neural Networks
    Young H. Oh (Sungkyunkwan University), Quan Quan, Daeyeon Kim, Seonghak Kim, Jun Heo (Seoul National University), Jaeyoung Jang (Sungkyunkwan University), Sung Jun Jung, Jae W. Lee (Seoul National University)
  • E-PUR: An Energy-Efficient Processing Unit for Recurrent Neural Networks
    Franyell Silfa, Gem Dot, Jose Maria Arnau, Antonio Gonzalez (Polytechnic University of Catalonia)
RECEPTION
PACT 2018 Main Conference Day 2 - Friday, November 2, 2018
8:30-9:30 Keynote
Bettina Heim, Microsoft: "Quantum Computing - Vision and Reality"
8:30-10:00 BREAK
10:00-11:30 Session 4a: Runtime
  • Mage: Online Interference-Aware Scheduling in Multi-Scale Heterogeneous Systems
    Francisco Romero (Stanford University), Christina Delimitrou (Cornell University)
  • GMOD: A Dynamic GPU Memory Overflow Detector
    Bang Di, Jianhua Sun, Hao Chen (College of Computer Science and Electronic Engineering, Hunan University), Dong Li (Department of Electrical Engineering and Computer Science, University of California, Merced)
  • On-The-Fly Workload Partitioning for Integrated CPU/GPU Architectures
    Younghyun Cho (Seoul National University), Florian Negele (ETH Zurich), Seohong Park, Bernhard Egger (Seoul National University), Thomas R. Gross (ETH Zurich)
Session 4b: Storage Systems
  • 3D-XPath: High-Density Managed DRAM Architecture with Cost-effective Alternative Paths for Memory Transactions
    Sukhan Lee (Seoul National University), Kiwon Lee (Samsung), Minchul Sung (Seoul National University), Mohammad Alian (UIUC), Chankyung Kim, Wooyeong Cho, Reum Oh, Seongil O (Samsung),Jung Ho Ahn (Seoul National University), Nam Sung Kim (Samsung)
  • Attributed Consistent Hashing for Heterogeneous Storage Systems
    Jiang Zhou, Yong Chen (Texas Tech University)
  • DART: Distributed Adaptive Radix Tree for Efficient Affix-based Keyword Search on HPC Systems
    Wei Zhang (Texas Tech University), Houjun Tang, Suren Byna (Lawrence Berkeley National Laboratory), Yong Chen (Texas Tech University)
11:30-13:00 LUNCH
13:00-15:00 Best Paper Session
  • Cost Effective Speculation with the Omnipredictor
    Arthur Perais (Qualcomm), André Seznec (Inria)
  • Towards Concurrency Race Debugging: An Integrated Approach of Constraint Solving and Dynamic Slicing
    Long Zheng, Xiaofei Liao, Hai Jin (Huazhong University of Science and Technology), Bingsheng He(National University of Singapore), Jingling Xue (University of New South Wales), Haikun Liu (Huazhong University of Science and Technology)
  • Optimizing Remote Data Transfers in X10
    Arun T, V Krishna Nandivada (IIT Madras)
  • Near-Side Prefetch Throttling: Adaptive Prefetching for High-Performance Many-Core Processors
    Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur (Intel Corporation)
15:00-21:00 Excursion
PACT 2018 Main Conference Day 3 - Saturday, November 3, 2018
8:30-9:30 Keynote
Natalie Enright Jerger, University of Toronto: "Architecting Chiplet-Based Systems"
9:30-10:00 BREAK
10:00-10:50 ACM Student Research Competition Presentations
10:50-12:50 Session 5a: Programming Models & Compilers
  • ComP-Net: Command Processor Networking for Efficient Intra-kernel Communications on GPUs
    Michael LeBeane (AMD/ UT Austin), Khaled Hamidouche, Brad Benton (AMD), Mauricio Breternitz (Instituto Universitario de Lisboa), Steven K. Reinhardt (Microsoft), Lizy K. John (UT Austin)
  • Cimple: Instruction and Memory Level Parallelism DSL
    Vladimir Kiriansky, Haoran Xu, Martin Rinard, Saman Amarasinghe (MIT CSAIL)
  • Automatic Identification and Annotation of Tasks in Structured Programs
    Pedro Ramos, Gleison Mendonça, Guilherme Leobas (UFMG), Divino César, Guido Araújo (Unicamp), Fernando Magno Quintão Pereira (UFMG)
  • Cost-Driven Thread Coarsening for GPU kernels
    Prithayan Barua, Jun Shirako, Vivek Sarkar (Georgia Institute of Technology)
Session 5b: Memory and Acceleration
  • Transactional Pre-abort Handlers in Hardware Transactional Memory
    Sunjae Park (Georgia Institute of Technology), Christopher J. Hughes (Intel), Milos Prvulovic (Georgia Institute of Technology)
  • In-DRAM Near-Data Approximate Acceleration for GPUs
    Amir Yazdanbakhsh (Georgia Institute of Technology), Choungki Song (University of Wisconsin-Madison), Jacob Sacks (Georgia Institute of Technology), Pejman Lotfi-Kamran (Institute for Research in Fundamental Sciences (IPM)), Nam Sung Kim (University of Illinois at Urbana–Champaign), Hadi Esmaeilzadeh (University of California - San Diego)
  • Biased Reference Counting: Limiting Atomic Operations in Reference Counting
    Jiho Choi, Thomas Shull, Josep Torrellas (University of Illinois at Urbana-Champaign)
  • Hybrid Optimization/Heuristic Instruction Scheduling for Programmable Accelerator Codesign
    Tony Nowatzki (UCLA), Newsha Ardalani (University of Wisconsin, Madison), Jian Weng (UCLA), Karthikeyan Sankaralingam (University of Wisconsin, Madison)
12:50-13:00 Awards Presentation
13:00 Adjourn